Adaptation of the pseudo-metal–oxide–semiconductor field effect transistor technique to ultrathin silicon–on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling

Abstract

This paper revisits and adapts of the pseudo-MOSFET (Ψ-MOSFET) characterization technique for advanced fully depleted silicon on insulator (FDSOI) wafers. We review the current challenges for standard Ψ-MOSFET set-up on ultra-thin body (12 nm) over ultra-thin buried oxide (25 nm BOX) and propose a novel set-up enabling the technique on FDSOI structures. This novel configuration embeds 4 probes with large tip radius (100–200 μm) and low pressure to avoid oxide damage. Compared with previous 4-point probe measurements, we introduce a simplified and faster methodology together with an adapted Y-function. The models for parameters extraction are revisited and calibrated through systematic measurements of SOI wafers with variable film thickness. We propose an in-depth analysis of the FDSOI structure through comparison of experimental data, TCAD (Technology Computed Aided Design) simulations, and analytical modeling. TCAD simulations are used to unify previously reported thickness-dependent analytical models by analyzing the BOX/substrate potential and the electrical field in ultrathin films. Our updated analytical models are used to explain the results and to extract correct electrical parameters such as low-field electron and hole mobility, subthreshold slope, and film/BOX interface traps density.