Implementation of dual-direction SCR devices in analog CMOS process

Abstract

Implementation of the dual-direction SCRs in a 5 V analog CMOS process was studied using pulsed I-V measurements and numerical simulations. A positive feedback mechanism associated with a parasitic vertical PNP was found, discussed and further utilized to improve the SCR latch-up robustness. The 2kV HBM 200V MM ESD protection capabilities with the holding voltage exceeding 5V were demonstrated in the ESD cells with the footprint size smaller than 2100 sq. um.