A Screening Methodology for VMIN Drift in SRAM Arrays with Application to Sub-65nm Nodes

Abstract

SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues