A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS

Abstract

One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as the high path loss at mm-Wave frequencies demands higher EIRP, which in turn requires considerable design effort on the transmitter. In addition, to comply with the OFDM transmitting mode of the IEEE 802.15.3c standards, the power amplifier (PA) must be capable to handle a peak power level 6~9dB higher than the average without sacrificing reliability. With the low supply voltage limitation of deeply scaled CMOS technologies, efficient power-combining techniques are essential. Spatial power combining is an attractive solution to meet the EIRP goal, but at the cost of spending extra power on the complex signal distribution and in order to compensate for the phase-shifter loss. Spatial power-combining solutions also occupy larger area due to the requirement of multiple antennas, minimum antenna spacing, and the transmission line feed network. On the other hand, CMOS PAs with on chip power-combining structures have achieved 18dBm of output power. However, all the combiners comprise multiple stages to achieve both impedance transformation and power combining which not only increase the insertion loss and directly degrade the efficiency, but also consume a significant amount of silicon area, rendering them far less appealing for system integration. This paper presents a fully integrated 18.6dBm CMOS PA based on an efficient and compact on-chip power combiner.