Thick microporous silicon isolation layers for integrated RF inductors

Abstract

Abstract In this paper, we present processes to etch high thickness porous silicon layers for RF device applications. Indeed, on‐chip inductors realized on bulk silicon suffer from mediocre Q‐factor values mainly because of electrical losses into the substrate and capacitive coupling with the silicon appearing beyond 1 GHz. We present a detailed study of etching parameters such as the current density or the HF concentration in HF: H 2 O:acetic acid based electrolytes. In addition, we propose a prospective study of integrated copper inductor performances on porous silicon substrates in the range of 100 MHz to 10 GHz. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)