Fabrication of high performance 3C‐SiC vertical MOSFETs by reducing planar defects

Abstract

Abstract The planar defect density of 3C‐SiC can be reduced by growing it on undulant‐Si substrates. However, specific stacking faults (SFs) remain, that expose the Si‐face on the (001) surface. These residual SFs increase the leakage current in devices made with 3C‐SiC. They can be eliminated using an advanced SF‐reduction method called switch‐back epitaxy (SBE) that combines polarity conversion with homoepitaxial growth. Vertical metal–oxide–semiconductor field‐effect‐transistors (MOSFETs) are fabricated on 3C‐SiC with SBE, varying in size from a single cell with an area of (30 × 30) μm 2 to 12,000 hexagonal cells on a (3 × 3) mm 2 chip. The MOSFET characteristics suggest that currents greater than 100 A are realistic for blocking voltages of 600–1,200 V by increasing the number of cells with reduced cell‐pitch. The combination of blocking voltage capability with a demonstrable high current capacity shows that 3C‐SiC is well‐suited for use in vertical MOSFETs for high‐ and medium‐power electronic applications. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)