300-V High-Side Thin-Layer-SOI Field pLDMOS With Multiple Field Plates Based on Field Implant Technology

Abstract

A novel 300-V high-side thin-layer-SOI field pLDMOS adopting field implant (FI) technology and multiple field plates (MFPs) has been developed. Breakdown mechanisms of back gate (BG) punchthrough and avalanche breakdown for highside thin-layer-SOI field pLDMOS are investigated by setting up an analytic model, simulating, and verifying experimentally. Shallow junction depth of p-field achieved by the proposed FI technology attenuates BG punchthrough effect; premature surface avalanche breakdown can be avoided by using MFPs. High-side field pLDMOS with a breakdown voltage (BV) of 340 V is experimentally realized on a 1.5-μm -thick SOI layer and successfully applied in a 200-V high-voltage switching IC.