Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

TLDR

As CMOS technology scales below 90 nm, SRAM‑based FPGAs suffer high standby power from leakage, and while MRAM offers non‑volatility and fast access to enable power‑down of idle logic and runtime reconfiguration, conventional field‑induced MRAM suffers high power, area, and cell disturbance, limiting its adoption. This work evaluates spin‑transfer‑torque MRAM to overcome those limitations and proposes design techniques and a novel FPGA architecture based on STT‑MRAM. The authors implement the design in a 90 nm CMOS process using a STT‑MTJ spice model to simulate programming latency and power characteristics. Simulations show that the STT‑MRAM FPGA achieves low programming latency and power, demonstrating the expected performance benefits over conventional MRAM.

Abstract

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.