IEEE Transactions on Computers · 1972 · 74 citations · 9 references
EngineeringComputer EngineeringComputer ScienceFault-tolerant ComputingFault-tolerant SystemsLogicBuilt-in Self-testCombinational Logic DescriptionDesign For TestabilityDigital Logic DesignFault DetectionFault DiagnosisCombinational Logic DesignLogic Gate Networks
New techniques are presented for generating fault-detection experiments for combinational logic networks. Only single-output functions are considered. Test-covering and test-equivalence relations between networks are defined and these relations are shown to be Instrumental in generating the experiments. The techniques presented provide minimal experiments for detecting multiple faults In two-level networks and provide nearly minimal experiments for most other networks.
9