Effects of Electrostatically Doped Source/Drain and Ferroelectric Gate Oxide on Subthreshold Swing and Impact Ionization Rate of Strained-Si-on-Insulator Tunnel Field-Effect Transistors

Abstract

This letter reports an electrostatically doped source/drain (EDSD) ferroelectric strained-Si-on-insulator (Fe-SSOI) tunnel field-effect transistor (TFET) with the subthreshold swing (SS) as low as 10 mV/dec for sub-30 nm applications. The proposed device, named as EDSD Fe-SSOI TFET in this report, uses two metal electrodes of Pt and Hf placed at the two sides of the gate on a thin intrinsic (dopingless) strained-Si layer to convert the undoped strained-Si regions below the Pt and Hf electrodes into the respective p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drain regions (by plasma charge phenomenon) of the TFET using the ferroelectric stacked gate oxides. While the plasma charge concept provides the abrupt source (drain)-channel junction by avoiding dopant migration from the source (drain) to channel, the intrinsic channel makes the proposed TFET device free from the random dopant fluctuation-related problems. The combined effects of the ferroelectric stacked gate oxides and the strain in intrinsic-Si channel of the proposed TFET structure are observed to result in a significant improvement in the SS as well as the drain current of the proposed EDSD Fe-SSOI TFET under consideration.