Optimization of innovative approaches to the shortening of filling times in 3D integrated through-silicon vias (TSVs)

Abstract

The continuously decreasing size of integrated circuits is the driving force for the emergence of three-dimensional (3D) integration. The through-silicon via (TSV) is the heart of 3D IC/Si integrations, providing the shortest vertical interconnections, and it has a large number of significant advantages. In this paper, a new additive system specifically developed for high aspect ratio TSVs is introduced for TSV electroplating. A wafer is patterned using the deep reactive ion etching (DRIE) technique, and the seed layer is deposited using the physical vapor deposition (PVD) technique. Anode position optimization, a multi-step TSV filling process, additive concentration and plating current density optimization are conducted to enhance the filling efficiency while maintaining the void-free filling profile. The availability is verified by the wafer-segment plating of TSVs. The mechanism is investigated using linear sweep voltammetry (LSV), chronoamperometry, and a numerical simulation method.