Analysis of HCS in STI-based LDMOS transistors

Abstract

A numerical investigation of the hot-carrier behavior of a lateral DMOS transistor with shallow trench isolation (STI) is carried out. The measured drain-current degradation induced by hot-carrier stress (HCS) is nicely reproduced by TCAD results revealing that interface traps are mainly formed at the STI corner close to the channel. The effect of typical device design variations on hot-carrier degradation is analyzed.