High Transconductance MISFET With a Single InAs Nanowire Channel

Abstract

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BR</sub> > 3 V. The channel current divided by diameter <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> of an NW reaches 3 A/mm. A maximum normalized transconductance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m </i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.