Reliability Modeling and Management of Nanophotonic On-Chip Networks

TLDR

Nanophotonic on‑chip networks promise improved performance and energy efficiency, yet their sensitivity to fabrication and thermal variation creates significant integration challenges. The study aims to mitigate performance and reliability issues caused by these variations in nanophotonic on‑chip networks. The authors develop a model of thermal and process variation effects and demonstrate run‑time optimization methods to compensate these variations and enhance many‑core system performance and reliability.

Abstract

While transistor performance and energy efficiency have dramatically improved in recent years, electrical interconnect improvements has failed to keep pace. Recent advances in nanophotonic fabrication have made on-chip optics an attractive alternative. However, system integration challenges remain. In particular, the parameters of on-chip nanophotonic structures are sensitive to fabrication-induced process variation and run-time spatial thermal variation across the die. This work addresses the performance and reliability challenges that arise from this sensitivity to variation. The paper first presents a model predicting the system-level effects of thermal and process variation in nanophotonic networks. It then shows how to optimize many-core system performance and reliability by using run-time techniques to compensate for the thermal and process variation effects.