A dynamically reconfigurable computing model for video processing applications

Abstract

We introduce an idealized dynamically reconfigurable computing model that is suitable for applications in video processing applications. Dynamically reconfigurable computing is characterized by a dynamic data path which has been made possible with the partial reconfiguration feature available in modern FPGA devices. Dynamically reconfigurable computing design leads to a multi-objective optimization model with constraints on power, performance and resources. We provide a review of recent reconfigurable computing applications reported by different groups and propose a new model for dynamically reconfigurable video processing applications. We provide model measurements for reconfiguration time overhead, static and reconfiguration power consumption.