Differentiation of Effects due to Grain and Grain Boundary Traps in Laser Annealed Poly-Si Thin Film Transistors

Abstract

A new physical model based on two dimensional simulations for high quality laser re-crystallised poly-Si thin film transistors is presented. It has been shown that to adequately explain the improved subthreshold slope and the lack of saturation of the output characteristics in these transistors, it is essential to distribute the density of defect states between traps in the grains alongside traps localised at grain boundaries. A double exponential density of states has been extracted for thin film transistors (TFTs) annealed at different excimer laser energies, using the field effect conductance method. By splitting the density of states between grain traps and grain boundary traps good fits to the output characteristics have been achieved. Lack of saturation is shown to be due to decrease in potential barrier at grain boundaries with increase in drain bias. At high gate voltages, however, evidence of a self-heating effect similar to that observed in silicon-on-insulator (SOI) transistors is apparent.