17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

Abstract

Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</sub> ) and small I/O capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IO</sub> ) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.