Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

Abstract

We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 500 nm device has a excellent drive current of ~450 μA/μm and intrinsic transconductance of ~1000 μS/μm indicating that III-V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.