IEEE Transactions on Computers · 1977 · 64 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceFault-tolerant ComputingSemiconductor DevicesConfigurable Logic BlocksDesign For TestabilityHardware Fault ToleranceProgrammable Logic DevicesProgrammable Array LogicProgrammable Logic ArrayProgrammable Logic DesignSignals
This paper presents an LSI-oriented approach to computer-maintained rectangular arrays of programmable logic. No signal line connects more than a few cells. A loading mechanism in each cell allows a computer directly connected to one cell to load any good cell that is not walled off by flawed cells. A loading arm is grown by programming cells to form a path that carries loading information. Cell mechanisms allow a computer to monitor the growth of a loading arm, and to change the arm's route or retract the arm to avoid faulty cells. Properly loaded cells carry test signals between a tested cell and a testing computer directly connected to only a few cells. The computer discovers the faulty cells in an array, and repairs the array by loading the array's good cells. This allows a computer to embed a perfect, very reliable digital machine on an entire flawed semiconductor wafer.
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