IEEE Transactions on Electron Devices · 2009 · 212 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDevice ReliabilityDevice ScalingDevice SimulationSemiconductor ReliabilityCell GeometryDevice Scaling EffectsNand Flash MemoryRandom NoiseRandom Telegraph NoiseThreshold VoltageThreshold Voltage ModelingThreshold Voltage Scaling
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca–nanometer Flash memories, considering both the <emphasis emphasistype="smcaps">nor</emphasis> and the <emphasis emphasistype="smcaps">nand</emphasis> architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca–nanometer Flash memories. </para>
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RTS amplitudes in decananometer MOSFETs: 3-D simulation study
Asen Asenov, R. Balasubramaniam, A. R. Brown et al. · IEEE Transactions on Electron Devices · 2003 · 260 citations
Random telegraph noise in flash memories - model and technology scaling
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