High-Linearity CMOS T/R Switch Design Above 20 GHz Using Asymmetrical Topology and AC-Floating Bias

Abstract

This paper presents circuit techniques to achieve high linearity and good isolation for CMOS transmit/receive (T/R) switches above 20 GHz. A comparison between the conventional symmetrical and the proposed asymmetrical switch topology is presented with an emphasis on the linearity performance. The substrate loading effects on T/R switch figure of merit are analyzed quantitatively based on a compact model of triple-well (TW) NMOS device. AC-floating bias techniques used for the T/R switch and the associated performance tradeoffs are discussed. By combining these techniques, an LC-tuned 24-GHz single-pole double-throw T/R switch is implemented in a 90-nm TW CMOS process. The switch uses 1.2-V digital control signals for both T/R mode selection and source/drain biases. The design achieves a measured P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 28.7 dBm, which represents the highest linearity reported to date for CMOS millimeter-wave switches. The measured insertion loss and return loss at 24 GHz are better than 3.5 and 10 dB, respectively.