2010 · 37 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAgingMicroelectronicsSemiconductor DevicesBuilt-in Self-testDesign For TestabilityDevice ReliabilityMixed-signal Integrated Circuit DesignNoise In Electronic DevicesNoise In Semiconductor DevicesAging CharacterizationDegradation MonitoringNoise AnalysisNoise Analysis In Integrated CircuitsNoise ImmunityOn-chip InstrumentationReliability Degradation Mechanisms
We design an on-chip aging monitor that combines the advantages of the small area of a ring-oscillator-type monitor and the short measurement time of a delay-line type monitor. It offers 1) short measurement time (more than 10x faster than conventional aging monitors, 2) small size (1/6 the size of a delay-line monitor), and 3) strong VDD noise immunity.
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Impact of negative bias temperature instability on digital circuit reliability
V. Reddy, A.T. Krishnan, Andrew Marshall et al. · 2003 · 229 citations
Engineering, Computer Engineering, Electrical Engineering +14
Reliability challenges for 45nm and beyond
J. W. McPherson · 2006 · 161 citations
Engineering, Computer Engineering, Electrical Engineering +17