A 32nm tunnel FET SRAM for ultra low leakage

Abstract

This paper describes the applicability of Tunnel FETs to commercial embedded Static Random-Access Memories (SRAM). Numerical device simulations were used first to optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its stability is analyzed. Our novel 8T TFET SRAM cell operates at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1V. The Read and Write Static Noise Margins are evaluated at 120mV and 200mV, with the operation speed of 300MHz and 1GHz in read and write respectively. The cell leakage is less than 10fA at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1V. Our results show that TFETs are excellent candidates for embedded SRAMs due to their Ultra-Low Standby Power (LSTP).