2011 · 18 citations · 17 references
EngineeringComputer EngineeringLow-power DesignPower ElectronicsTest ConstructionBuilt-in Self-testDesign For TestabilityDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementPower OptimizationDigital Circuit Self-testingLow-power Design For TestabilityLow-power Test DesignPower ConsumptionPower-aware Built-in Self-testSwitching Activity AnalysisSwitching Activity ReductionTest Compression
This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of existing DFT logic, its use results in a low switching activity during all phases of scan test: loading, capture, and unloading. It reduces power consumption to or below a level of a functional mode, thus helping to resolve problems related to power dissipation, voltage drop, and increased temperature.
17
A test vector inhibiting technique for low energy BIST design
Patrick Girard, L. Guiller, C. Landrault et al. · 2003 · 157 citations
Engineering, Computer Engineering, Electrical Engineering +15