90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization

Abstract

Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High-resolution TDCs become increasingly popular for time-of-flight measurements, full-speed testing, e.g., jitter measurement, clock and data recovery, measurement and instrumentation, and digital PLLs. As the speed leverage of technology scaling decreases below 100nm, robust TDCs with sub-gate-delay resolution are essential. The Vernier TDC requires long delay lines, thus suffers from large latency, area and power consumption. Latency and a resolution limited by the inherent variation-related pulse-width modification are the drawbacks of the pulse-shrinking approach. Parallel gradual-delay elements are particularly susceptible to process variations. The same holds for analog operations on time intervals like delay amplification. Ultra high-resolution TDCs achieve sub-ps resolution but require iterative conversion.