The role of VHDL within the TOSCA hardware/software codesign framework

Abstract

VHDL-based cosimulation, starting from high-level cospecification. The prototype software environment, supporting the envisaged codesign flow, will also be addressed. This paper presents an overview of a hardware/software codesign methodology and its supporting framework (TOSCA) with emphasis on the role played by the VHDL language. The proposed approach is tailored for control-oriented applications and aims at capturing the entire codesign flow, including system cospecification, high-level partitioning, hw/sw tradeoffs, cosynthesis and cosimulation. 2. The codesign environment The proposed methodology aims at allowing computer-aided exploration of alternative system architectures in order to balance hardware cost/performance and software flexibility. A prototype software environment, supporting the codesign flow depicted in fig.1, is currently under development. The final goal is to cover all the following issues: VHDL acts as the cornerstone in the task of evaluating the outputs of the codesign flow as well as linking them to commercial simulation and synthesis environments. In particular, the paper will address the issue of simulating hardware/software architectures, focusing on the application of VHDL to the definition of an easily retargetable CPU core model by exploiting the concept of virtual kernel and customizable input/output management scheme. • acquisition of behavioral specifications, suited to the application field of interest, while maintaining full independence of any particular hw/sw implementation; • analysis/validation at specification-level; • tool-directed system-level partitioning including hw/sw binding of specifications;