A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC

Abstract

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3x3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive l/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.