A 40 Gb/s transimpedance amplifier in 65 nm CMOS

Abstract

A 40 Gb/s transimpedance amplifier (TIA) is designed as a modified regulated cascode in 65 nm CMOS technology using ultra-compact peaking inductors to provide improved frequency response and lower input referred noise. The bandwidth of the TIA is 21.6 GHz with 46.7 dBΩ of gain for an input capacitance of 200 fF and the simulated input referred noise is below 30pA/√(Hz) up to 26.1 GHz. The TIA core occupies only 150 μm×50 μm of chip area and for a 1.2 V supply voltage the TIA consumes 8.2 mW while the power-hungry buffers need 31.5 mW to drive the 50 Ω load. The TIA is measured in a 50 Ω environment.