A 40-Gb/s Transimpedance Amplifier in 0.18-$\mu$m CMOS Technology

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-<formula formulatype="inline"><tex>$\mu{\hbox {m}}$</tex></formula> CMOS technology. From the measured S-parameters, a transimpedance gain of 51 <formula formulatype="inline"> <tex>${\hbox {dB}}\Omega$</tex></formula> and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, <formula formulatype="inline"><tex>$\pi$</tex></formula>-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of <formula formulatype="inline"><tex>$\hbox{1.17}\times \hbox{0.46}\ {\hbox {mm}}^{2}$</tex></formula>. The proposed CMOS TIA presents a gain–bandwidth product per DC power figure of merit <formula formulatype="inline"> <tex>$({\rm GBP}/P_{\rm dc})$</tex></formula> of 180.1 <formula formulatype="inline"> <tex>${\hbox{GHz}}\Omega/{\hbox{mW}}$</tex></formula>. </para>