2014 · 132 citations · 32 references
EngineeringComputer ScienceHigh-performance ComputingComputer ArchitectureLow-power DesignSystem-on-chip DesignDevice ScalingLow-power Cache DesignPower ManagementPower OptimizationPower-aware DesignVoltage ScalingEnergy-efficient ArchitectureEnergy-efficient Hardware AccelerationEnergy-efficient Memory DesignPower ConsumptionPower Consumption OptimizationPower-aware Hardware ArchitecturePower-efficient ArchitectureVoltage Scaling In Memory Systems
Modern scientific discovery demands ever‑higher computing performance, and the HPC community aims to build 1‑ExaFlop supercomputers by 2020, but power consumption is the main obstacle, requiring over 20× energy‑efficiency gains from architectural, circuit, and manufacturing advances. The paper presents NVIDIA Research’s progress toward Exascale system design, tailoring features to meet performance and energy‑efficiency scaling challenges. The authors evaluate architectural concepts for HPC applications, showing energy‑efficiency gains from innovations such as low‑voltage SRAM, low‑energy signalling, and on‑package memory, and project how these features scale with future process technologies to deliver power and performance targets for their Exascale research architecture.
Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signalling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.
32
William J. Dally, Brian Towles · 2001 · 3.2K citations
Engineering, Computer Engineering, Electrical Engineering +17
Dark silicon and the end of multicore scaling
Hadi Esmaeilzadeh, Emily Blem, Renée St. Amant et al. · 2011 · 1.5K citations
NVIDIA Tesla: A Unified Graphics and Computing Architecture
Erik Lindholm, John Nickolls, Stuart F. Oberman et al. · IEEE Micro · 2008 · 1.3K citations
GPUs and the Future of Parallel Computing
Stephen W. Keckler, William J. Dally, Brucek Khailany et al. · IEEE Micro · 2011 · 664 citations
Dark Silicon and the End of Multicore Scaling
Hadi Esmaeilzadeh, Emily Blem, Renée St. Amant et al. · IEEE Micro · 2012 · 491 citations