Scaling the Power Wall: A Path to Exascale

TLDR

Modern scientific discovery demands ever‑higher computing performance, and the HPC community aims to build 1‑ExaFlop supercomputers by 2020, but power consumption is the main obstacle, requiring over 20× energy‑efficiency gains from architectural, circuit, and manufacturing advances. The paper presents NVIDIA Research’s progress toward Exascale system design, tailoring features to meet performance and energy‑efficiency scaling challenges. The authors evaluate architectural concepts for HPC applications, showing energy‑efficiency gains from innovations such as low‑voltage SRAM, low‑energy signalling, and on‑package memory, and project how these features scale with future process technologies to deliver power and performance targets for their Exascale research architecture.

Abstract

Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signalling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.