Proposed model for bistability in nanowire nonvolatile memory

V. I. Pokalyakin, S. A. Tereshin, A. Varfolomeev, D.F. Zaretsky, Alexander Baranov, Amit Banerjee, Y. Wang, Sivakumar Ramanathan, S. Bandyopadhyay

Journal of Applied Physics · 2005 · 16 citations · 5 references

Concepts

Abstract

Cadmium sulfide nanowires of 10-nm diameter, electrodeposited in porous anodic alumina films, exhibit an electronic bistability that can be harnessed for nonvolatile memory. The current–voltage characteristics of the wires show two stable conductance states that are well separated (conductances differ by more than four orders of magnitude) and long lived (longevity>1yr at room temperature). These two states can encode binary bits 0 and 1. It is possible to switch between them by varying the voltage across the wires, thus “writing” data. Transport behavior of this system has been investigated at different temperatures in an effort to understand the origin of bistability, and a model is presented to explain the observed features. Based on this model, we estimate that about 40 trapped electrons per nanowire are responsible for the bistability.

References

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