IEICE Electronics Express · 2008 · 16 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDigital Integrated CircuitsDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignTiming AnalysisAdder DesignAddersLow-power Arithmetic CircuitsMultiplier DesignPower ConsumptionPower Consumption ModelingPower-delay ProductPower-delay Tradeoff
Two novel 1-bit Full Adder cells based on Majority Function and the similarity between the minterms of the Cout and Sum functions, are proposed. The cells offer higher speed and less Power-Delay Product (PDP) than the conventional and current implementations of the 1-bit Full Adder cells especially in low voltages. All the input patterns are used for simulation to obtain the delay and the power consumption parameters. Simulations demonstrate improvement in terms of PDP and significant improvement in terms of speed.
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Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
Keivan Navi, Omid Kavehei, Mahnoush Rouholamini et al. · Journal of Computers · 2008 · 104 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17