An on-chip waveform capturing technique pursuing minimum cost of integration

Abstract

An on-chip waveform capturing technique demonstrates 8.5 ENOB and 62.7 dB SFDR at 200 Ms/s for analog signals with 25-MHz bandwidth and 2.5 V rail-to-rail offset DC level, suitable for testing and self diagnosis of a mixed-signal chip. The area of 0.004mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 90 nm CMOS chip is only required for the integration of probing front end circuitry, with the help of an efficient discretization algorithm on a digital data processing chain involving on-chip logic paths, an off-chip 8 bit micro controller, and PC. Waveform acquisition at the system throughput of 1.9 transaction/point is achieved, by minimizing the number of slow-speed transactions between external measurement equipments and PC.