Iterated interpolation using a systolic array

Abstract

An implementation using systolic array logic of Aitken's method of iterated interpolation is described. The proposed design has a simple, linear topology, requires no clock, and makes only modest demands on the host computer. By overlapping the computation of successive function values, a processing element utilization of approximately 1/2 is achieved. The paper illustrates how “mathematical hardware” packages, as well as software library routines, may be part of the mathematical problem solver's tool kit in the future.