Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Abstract

A growing number of processing cores on a chip require an efficient and scalable communication structure such as network on chip (NoC). The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system. Dynamically allocated multiqueues (DAMQs) are an effective mechanism to achieve VC flow control with maximum buffer utilization. In this model, VCs employ variable number of buffer slots depending on the traffic. Despite the performance merits of DAMQs, it has some limitations. We propose a new input-port microarchitecture to support our efficient dynamic VC (EDVC) approach that is built on DAMQ buffers. To demonstrate the advantages of EDVC, we compare its microarchitecture with that of the conventional dynamic VC (CDVC), which also employs link-list tables for buffer organization. In terms of hardware, EDVC input-port organization consumes on average 61% less power for application-specific integrated circuit design when compared with the CDVC input port. The saving is even better when compared with VC regulator methodology. An EDVC approach can improve NoC latency by 48%-50% and throughput by 100% on average as compared with the CDVC mechanism.