A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown

Abstract

This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> time constant of less than 500ps, and is shown to handle a 19V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.