Minimization of germanium penetration, nanocrystal formation, charge storage, and retention in a trilayer memory structure with silicon nitride/hafnium dioxide stack as the tunnel dielectric

Abstract

Trilayer structures, consisting of a rapid thermal oxide (RTO) layer (2.5 or 5 nm thick) grown on silicon, a sputtered Ge middle layer (3–20 nm thick), and a 50-nm-thick sputtered silicon oxide capping layer, exhibit significant penetration of Ge atoms into the silicon substrate for devices with the smaller (2.5 nm) RTO thickness, resulting in negligible nanocrystal formation and hence no charge storage or memory effect. The Ge penetration is minimized by replacing the RTO layer with a high dielectric constant (high-κ) silicon nitride/hafnium dioxide stack (grown by metalorganic chemical vapor deposition) having a larger physical thickness but smaller equivalent oxide thickness of 1.9 nm. Results show that the high-κ trilayer structure exhibits better charge storage capability (in terms of a lower program voltage) and better charge retention performance as compared to the RTO trilayer structure.