IEEE Design & Test of Computers · 1987 · 55 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingReconfigurable ComputingAccelerator ArchitectureField-programmable Gate Array ArchitectureHardware AccelerationMulticore Processor DesignParallel ArchitecturesReconfigurable AcceleratorsAccelerator MicroarchitectureAcceleratorsField-programmable Gate Array AccelerationField-programmable Gate Array AcceleratorsMicroarchitectural SimulationParallel Computing ArchitecturesProgrammable AcceleratorsSimulation Acceleration
MARS, short for microprogrammable accelerator for rapid simulations, is a multiprocessor-based hardware accelerator that can efficiently implement a wide range of computationally complex algorithms. In addition to accelerating many graph-related problem solutions, MARS is ideally suited for performing event-driven simulations of VLSI circuits. Its highly pipelined and parallel architecture yields a performance comparable to that of existing special-purpose hardware simulators. MARS has the added advantage of flexibility because its VLSI processors are custom-designed to be microprogrammable and reconfigurable. When programmed as a logic simulator, MARS should be able to achieve 1 million gate evaluations per second.
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The Second Generation MOTIS Mixed-Mode Simulator
C. F. Chen, CY Lo, H. N. Nham et al. · Design Automation Conference · 1984 · 56 citations
Engineering, Computer Engineering, Electrical Engineering +17
The Second Generation MOTIS Mixed-Mode Simulator
C.F. Chen, Chi-Yuan Lo, H. N. Nham et al. · 21st Design Automation Conference Proceedings · 1984 · 47 citations
Engineering, Computer Engineering, Electrical Engineering +17