Field-Programmable Gate Array Acceleration is a hardware acceleration technique that leverages reconfigurable logic fabric to implement customized, application-specific parallel processing pipelines directly on a Field-Programmable Gate Array, distinguishing it from fixed-architecture accelerators by its post-fabrication programmability and fine-grained spatial parallelism.
556
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19.8K
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Authors
537
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Publications per year
2017–2026
238
Variants
Fpga Acceleration
Parents
Publications
556
The Garp architecture and C compiler
Timothy J. Callahan, John R. Hauser, John Wawrzynek · Computer · 2000 · 391 citations
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Authors
1.9K
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Institutions
537
Imperial College London
London, United Kingdom
19 h-index
66 publications
2.4K citations
University of Toronto
Toronto, Canada
13 h-index
39 publications
1.9K citations
Tsinghua University
Beijing, China
12 h-index
52 publications
1.7K citations
University of Southern California
Los Angeles, United States
12 h-index
28 publications
1K citations
University of California, Los Angeles
Los Angeles, United States
11 h-index
38 publications
1K citations
Boston University
Boston, United States
11 h-index
36 publications
2.2K citations
Chinese Academy of Sciences
Beijing, China
10 h-index
33 publications
1.4K citations
Nanyang Technological University
Singapore, Singapore
9 h-index
20 publications
724 citations
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Venues
- IEEE Access
23 publications · 769 citations
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
22 publications · 1.3K citations
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
21 publications · 961 citations
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- ACM Transactions on Reconfigurable Technology and Systems
12 publications · 608 citations
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- Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
11 publications · 414 citations
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