The Garp architecture and C compiler

TLDR

Various projects have used off‑the‑shelf FPGAs as computation accelerators, but long reconfiguration times, low‑bandwidth data paths, and the need for hardware design expertise limit their general usefulness. The authors aim to evaluate the viability of connected FPGA systems by designing the Garp architecture and testing application execution. They implemented Garp and conducted experiments to assess its ability to support automatic, fast, effective compilation across diverse applications. They present their results in this article.

Abstract

Various projects and products have been built using off-the-shelf field-programmable gate arrays (FPGAs) as computation accelerators for specific tasks. Such systems typically connect one or more FPGAs to the host computer via an I/O bus. Some have shown remarkable speedups, albeit limited to specific application domains. Many factors limit the general usefulness of such systems. Long reconfiguration times prevent the acceleration of applications that spread their time over many different tasks. Low-bandwidth paths for data transfer limit the usefulness of such systems to tasks that have a high computation-to-memory-bandwidth ratio. In addition, standard FPGA tools require hardware design expertise which is beyond the knowledge of most programmers. To help investigate the viability of connected FPGA systems, the authors designed their own architecture called Garp and experimented with running applications on it. They are also investigating whether Garp's design enables automatic, fast, effective compilation across a broad range of applications. They present their results in this article.