2010 · 13 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsDigital CommunicationMicroelectronicsClock Distribution NetworksClock ManagementMixed-signal Integrated Circuit DesignClock Network ArchitectureDuty Cycle CorrectionHigh-speed Cmos DesignHigh-speed I/o Circuit DesignHigh-speed I/o Signaling
To achieve high speed data signaling rates with the internal fast clock operating at half its speed,the XDR (extreme data rate) I/O link employs dual-edge signaling where in data bits are transmitted on both the edges (rise/fall) of transmit clock. Duty cycle correction technique is used to provide high frequency low jitter clocks that have 50% duty cycle. This paper compares two different techniques to implement duty cycle corrector (DCC). These techniques are implemented in high speed I/O operating at data rate of 4Gbps and 6.4Gbps in TSMC 65nm & TSMC 40nm technology achieving an output duty cycle error below ±2% for ±10% input duty cycle error.
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Clocking circuits for a 16Gb/s memory interface
Ting Wu, Xudong Shi, Kambiz Kaviani et al. · 2008 · 19 citations
A 500MHz DLL with second order duty cycle corrector for low jitter
Byung-Guk Kim, Kwang‐Il Oh, Lee-Sup Kim et al. · 2006 · 18 citations