A 500MHz DLL with second order duty cycle corrector for low jitter

Abstract

A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13/spl mu/m CMOS process achieves an output duty error below /spl plusmn/1.6% within /spl plusmn/25% external input duty error. It has a 29.2 ps peak-to-peak jitter and a 3.8 ps RMS jitter.