Realization of low contact resistance close to theoretical limit in graphene transistors

Abstract

Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. Furthermore, the contact resistance shows no clear dependence on temperature in the range of 77–300 K; this is attributed to the saturation of carrier injection efficiency between graphene and Pd owing to the high quality of the graphene samples used, which have a sufficiently long carrier mean-free-path.