Design of low power multiplier using reversible logic gate

Abstract

The reversible logic has received great attention in last few years due to their ability to decrease the power dissipation which is the main requirement in low power VLSI design. The traditional set of gates like AND, OR and EXOR are not reversible. This paper proposes a 4×4 bit reversible multiplier circuit using Peres gate which can multiply two 4-bit numbers. It is faster and has low hardware complexity compared to the existing designs. In addition, this reversible multiplier is better than the existing counterparts in terms of delay and power because the Peres gate reduces the garbage output. It is based on the two concepts, The partial products can be generated in parallel using Peres gates and thereafter the addition is done of all product terms by using reversible parallel adder designed from TSG gates. After that we replace the reversible parallel adder by modified reversible adder then we compare both the multiplier and compare the terms like garbage outputs, power dissipation, number of gates required and number of constant inputs. Thus, this paper provides the comparison of two multipliers according to their garbage outputs, power dissipation, number of gates required and number of constant inputs.