IEEE Journal of Solid-State Circuits · 1973 · 14 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignClock ManagementCmos Circuit DesignMemory DevicesMemory Subsystem DesignDynamic Random-access MemoryDynamic Random-access Memory DesignMemory Circuit DesignNon-volatile Memory DesignRandom Access Memory (Ram)Random-access Memory
Presents one version of a 4K dynamic MOS random-access memory utilizing a 3 device/bit cell with an area of less than 2 mil/SUP 2//b, which is fabricated using an n-channel silicon gate MOS technology. The chip requires only a single phase clock and internally generates the multiphase timing required. Other than the single high voltage clock, all inputs and the output are TTL compatible.
6
L. Vadasz, Andrew S. Grove, Tyler Rowe et al. · IEEE Spectrum · 1969 · 85 citations
Engineering, Computer Engineering, Electrical Engineering +16
A three transistor-cell, 1024-bit, 500 NS MOS RAM
W.M. Regitz, J. Karp · 1970 · 38 citations
Engineering, Computer Engineering, Electrical Engineering +16
J. Karp, W.M. Regitz · 1972 · 23 citations
Engineering, Computer Engineering, Electrical Engineering +15