2006 · 35 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign OptimizationLow-power DesignCombinatorial OptimizationHardware-software PartitioningLayout OptimizationMemory Hierarchy DesignPhysical DesignVery-large-scale Integration LayoutCongestion EstimationPlacementPlacement AlgorithmsPlacement OptimizationSimulated AnnealingStandard Cell PlacementStandard CellsWirelength Optimization
In this paper, we develop a mixed-size placement tool, Dragon2006, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partitioning and simulated annealing is used to place very large SoC-style designs containing fixed blockage, movable macro blocks of various sizes and standard cells. Moreover, we have applied several techniques for wirelength optimization, congestion estimation in the presence of blockage and white space allocation for congestion removal.
9
Multilevel hypergraph partitioning
George Karypis, Rajat Aggarwal, Vipin Kumar et al. · 1997 · 718 citations · Full text
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi · 2005 · 93 citations