A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

TLDR

Phase‑change random‑access memory (PRAM) is a promising, scalable, and cost‑effective future memory technology, yet its low chip density and limited write bandwidth hinder system performance, despite research into application‑oriented uses that show power and cost benefits. This work introduces an 8‑gigabit PRAM that achieves 40 MB/s write bandwidth through an 8‑megabit sub‑array core architecture built with 20 nm diode‑switched cells. The design employs a 20 nm diode‑switched PRAM cell array arranged in an 8‑megabit sub‑array core to deliver the target 40 MB/s write throughput. Applying an external high voltage extends the write bandwidth to 133 MB/s.

Abstract

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.