Simulation of Worst-Case Total Dose Radiation Effects in CMOS VLSI Circuits

Abstract

A new methodology for evaluating worst-case radiation failure levels for CMOS VLSI circuits in total dose environments is presented. The new methodology reduces computation time by orders of magnitude by using simple calculations to identify vulnerable sub-circuits and worst-case irradiation and operating bias conditions. Sensitive sub-circuits are then analyzed by accurate, device-level simulators to predict radiation failure levels. The method has been implemented and results for sample circuits are described.