A critique of network speed in VLSI models of computation

Abstract

Evaluates various proposed VLSI models of computation. While there is a consensus on the appraisal of chip area, controversy remains with regard to computation time. Thus, the authors have analyzed in detail the propagation of signals on disperse lines. The results are expressed in terms of adimensional parameters characteristic of any given fabrication technology. The conclusion is that both current and projected silicon technologies fall within the realm of the capacitive model where a dispersive line can be replaced by a capacitance proportional to its length. Diffusion phenomena therefore appear to exceed the present VLSI horizon.