ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS

A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN

F. Brglez · Medical Entomology and Zoology · 1985 · 1.3K citations

Engineering, Computer Engineering, Computer Science +10

An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

 Goel · IEEE Transactions on Computers · 1981 · 1.1K citations

Engineering, Computer Engineering, Computer Science +12

A Switch-Level Model and Simulator for MOS Digital Systems

Bryant · IEEE Transactions on Computers · 1984 · 391 citations

Engineering, Computer Engineering, Electrical Engineering +17

Extraction and simulation of realistic CMOS faults using inductive fault analysis

F.J. Ferguson, John Paul Shen · 2003 · 256 citations

Engineering, Computer Engineering, Electrical Engineering +12

Bridging and Stuck-At Faults

K.C.Y. Mei · IEEE Transactions on Computers · 1974 · 239 citations

Engineering, Computer Engineering, Electrical Engineering +9